;---------------------------------------------------------------------------------------
; USB Boot Tool Configuration File. The tool will read the USBBoot.cfg
; to get the hardware configuration of your target board.
;
; This is an sample configuration file for the Jz4750 APUS board.
; If you are using a different board, please rename USBBoot_BOARD.cfg to USBBoot.cfg.
; If you modify the hardware of your board, modify the values in this file accordingly.
;
; First of all, you should install the driver when you boots the device from USB
; for the first time.
;
; The line starting with ';' or contents followed by ';' of a line are comments only.
;---------------------------------------------------------------------------------------

[PLL]
EXTCLK			12			;Define the external crystal in MHz
CPUSPEED		336			;Define the PLL output frequency
PHMDIV			3			;Define the frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK
BOUDRATE		57600			;Define the uart boudrate
USEUART			0			;Use which uart, 0/1 for jz4740,0/1/2/3 for jz4750

[SDRAM]
BUSWIDTH		16			;The bus width of the SDRAM in bits (16|32)
BANKS		  	4			;The bank number (2|4)
ROWADDR	  		12			;Row address width in bits (11-13)
COLADDR	  		9			;Column address width in bits (8-12)
ISMOBILE	  	0			;Define whether SDRAM is mobile SDRAM, this only valid for Jz4750 ,1:yes 0:no
ISBUSSHARE	  	1			;Define whether SDRAM bus share with NAND 1:shared 0:unshared

[NAND]
BUSWIDTH		8			;The width of the NAND flash chip in bits (8|16|32)
ROWCYCLES		3			;The row address cycles (2|3)
PAGESIZE		2048			;The page size of the NAND chip in bytes(512|2048|4096)
PAGEPERBLOCK		64 			;The page number per block
FORCEERASE		0			;The force to erase flag (0|1)
OOBSIZE			64			;oob size in byte
ECCPOS         		28			;Specify the ECC offset inside the oob data (0-[oobsize-1])
BADBLACKPOS     	0			;Specify the badblock flag offset inside the oob (0-[oobsize-1])
BADBLACKPAGE    	127   			;Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
PLANENUM		1			;The planes number of target nand flash
BCHBIT	  		4			;Specify the hardware BCH algorithm for 4750 (4|8)
WPPIN			0			;Specify the write protect pin number
BLOCKPERCHIP		0			;Specify the block number per chip,0 means ignore

[END]

;The program will calculate the total SDRAM size by : size = 2^(ROWADDR + COLADDR) * BANKNUM * (SDRAMWIDTH / 4)
;The CPUSPEED has restriction as: ( CPUSPEED % EXTCLK == 0 ) && ( CPUSPEED % 12 == 0 )
;For jz4750, the program just init BANK0(DSC0).
;Beware all variables must be set correct!